The present invention relates to a pattern designing method of extracting a resistance value and a capacitance value as electrical characteristics of a semiconductor circuit from design data of a semiconductor integrated circuit, and carrying out a timing verification, a pattern designing program, and a pattern designing apparatus.
The progress of the recent semiconductor manufacturing technology is very remarkable, and thus the semiconductor devises each having a minimum process dimension of 0.1 μm or less have been mass-produced. Along with the scale down of such semiconductor devices, there is caused such a problem that the semiconductor devices are not manufactured so as to fulfill the intended performance due to an influence of a process dispersion which did not become a problem in the previous generations.
A layout fidelity and timing convergence directly receive the influence of the process dispersion. In order to solve the problem about the layout fidelity, an optical proximity correction (OPC) technique for previously adding an auxiliary pattern to a design pattern so that a dimension after completion of the fabrication process fulfills a desired pattern, a process proximity correction (PPC) technique (hereinafter referred to as “a PPC technique”) or the like is reported as one of the method of enhancing the layout fidelity in Japanese Patent Laid-Open No. Hei 9-319067 referred to as Patent Document 1 hereinafter.
On the other hand, the problem about the timing convergence is described as follows. That is to say, a problem that misfit between design data and a transferred image on a wafer substrate causes an extraction precision to become worse in the stage for extracting the characteristics comes to be of particular note. In such a situation, a problem that a difference in fine shape between a design pattern and a transferred image when the design pattern is transferred onto a wafer substrate exerts a bad influence on the timing convergence owing to a process fluctuation becomes more acute along with the scale down of the semiconductor devices.
At present, in addition to the two problems described above, a thickness dispersion generated in a longitudinal structure (cross-sectional structure) of the device, or the like has to be taken into consideration when the capacitance value is extracted from the design data. That is to say, as apparent from FIG. 7, a consideration about the layout means a consideration about the x-y cross section, and a consideration about the cross-sectional structure means a consideration about the device in an x-z direction. Since there is actually the process fluctuation, a transferred image on a wafer substrate in the layout of an x-y plane has to be taken into consideration.
On the other hand, in a cross-sectional structure as well in the x-z direction, a film thickness disperses due to the process fluctuation, thus resulting in a dispersion being contained in each of layers. Therefore, how to take such fluctuations in the x-y and x-z directions in a technology file from which the capacitive value is extracted becomes a point for realizing the high precision.
The following method is known as one of the techniques which have been proposed up to this day for the purpose of promoting the high precision for the capacitance value extraction. That is to say, the pattern is designed in accordance with the design correction rules allowing for the electrical characteristics of the circuit, and the mask data is created for the design data so that the design pattern thus produced fulfills a margin for the process. This method, for example, is described in Japanese Patent Laid-Open No. 2006-038896 referred to as Patent Document 2 hereinafter. The electrical characteristics described above, for example, mean the capacitance value of the circuit. Thus, the design pattern is created so as to fulfill the specification about the predetermined capacitance value. Also, the mask pattern is created so that the image of the design pattern transferred onto the wafer substrate fulfills the process margin associated with the specification fulfilling the electrical characteristics.
In addition, Japanese Patent Laid-Open No. 2001-230323 referred to as Patent Document 3 hereinafter proposes the following technique. That is to say, the data on the difference between the shape on the wafer substrate after completion of the etching and the design pattern is previously prepared for the design pattern by using the test pattern. Also, the correspondence is made for that difference in accordance with the dimension in the layout which is actually processed, thereby creating the circuit pattern in which the finished dimension on the wafer substrate is reflected. Thus, the data on the resulting circuit pattern is then inputted to an extraction tool.
FIG. 8 is a flow chart showing a flow of typical processing in the techniques described above. According to those techniques, the design pattern can be corrected or the mask pattern data can be created so as to fulfill the predetermined capacitance value. As a result, it is possible to avoid the layout which becomes a problem in terms of the electrical characteristics.
In addition thereto, the extraction can be carried out by using the layout after measures have been taken to cope with a portion which became a problem in terms of the characteristics. That is to say, the electrical characteristics are calculated (Step S802) by using the physical layout (Step S805) for which the correction processing has been executed in the flow chart of FIG. 8. Each of the techniques disclosed in Patent Documents 2 and 3 described above is an approach for taking measures to cope with the layout on the X-Y plane of FIG. 7, creating the typical layout on the x-y plane, and carrying out the extraction so as to correspond to the cross-sectional structure about the x-z plane.